1. Technical Field
This disclosure generally relates to design of integrated circuit (IC) chips. More specifically, this disclosure relates to methods and systems for high-bandwidth on-chip communication.
2. Related Art
On-chip global wires are becoming an increasingly serious concern in current microprocessor designs in terms of latency, bandwidth, and power consumption. A simple yet effective solution to improve the latency of on-chip wires is to use repeaters, but the number of repeaters that are required and the power consumption of the repeaters are increasing with each technology step.
A number of approaches have been proposed to improve communication performance and reduce power consumption of global on-chip wires. In one such approach, transmission lines are used to offer near speed-of-light latency and high bandwidth. However, this approach requires considerably more wire resources, which results in poor bandwidth density (Gb/s/μm). Another approach uses current sensing techniques to reduce latency and improve bandwidth, but such approaches suffer from high static power consumption, which can negate the latency and bandwidth improvements. Some approaches use a pre-emphasis technique to reduce inter-symbol-interference (ISI) and improve data rate. Unfortunately, the energy consumption in these approaches can be too high even when no data activity is present because the energy consumption does not scale with data activity.
Approaches that drive a wire capacitively can increase on-chip wire bandwidth by capacitive pre-emphasis and enable low-swing signaling without requiring a second supply. Unfortunately, the latencies in these approaches are worse than the latencies of optimally repeated wires in scaled technology nodes with narrow wires. Moreover, the bandwidth in these approaches is severely limited by the slow slew rates of receiver-end signals.
Hence, what is needed are methods and systems for improving bandwidth of on-chip wires without the above-described drawbacks.